The present invention generally relates to recognizing structure information in netlists.
The design process for creating a circuit design typically includes phases of design entry, synthesis, and physical implementation. The physical implementation phase further breaks down into technology mapping and placing and routing (xe2x80x9cplace-and-routexe2x80x9d). At different stages in the design process the design is simulated to verify functional correctness and to verify that timing constraints are met.
Various design tools are used to functionally specify the design in the design entry phase, for example, schematic capture and HDL-based tools. At this design level the design is usually highly structured from a functional standpoint. The structure information is generally not carried forward in the output of synthesis tools. A synthesis tool generates a netlist that embodies the design specified in design entry, the netlist specifying components of the design and connectivity between the components.
The physical implementation tools process the netlist to produce design data suitable for building or configuring a particular device, for example, an ASIC or an FPGA. Because structure information is typically unavailable during physical implementation, the physical implementation tools may rely on heuristics, thereby creating problems in finding an optimal implementation. Some of the structure information might be helpful in effectively placing and routing the design.
A method and an apparatus that address the aforementioned problems, as well as other related problems, are therefore desirable.
The present invention in various embodiments provides for recognition of data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.